-
Notifications
You must be signed in to change notification settings - Fork 3
/
NanGate_15nm_OCL_conditional_2018_Aug_23.v
1819 lines (1472 loc) · 44.1 KB
/
NanGate_15nm_OCL_conditional_2018_Aug_23.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
//
// ******************************************************************************
// * *
// * Copyright (C) 2004-2014, Nangate Inc. *
// * All rights reserved. *
// * *
// * Nangate and the Nangate logo are trademarks of Nangate Inc. *
// * *
// * All trademarks, logos, software marks, and trade names (collectively the *
// * "Marks") in this program are proprietary to Nangate or other respective *
// * owners that have granted Nangate the right and license to use such Marks. *
// * You are not permitted to use the Marks without the prior written consent *
// * of Nangate or such third party that may own the Marks. *
// * *
// * This file has been provided pursuant to a License Agreement containing *
// * restrictions on its use. This file contains valuable trade secrets and *
// * proprietary information of Nangate Inc., and is protected by U.S. and *
// * international laws and/or treaties. *
// * *
// * The copyright notice(s) in this file does not indicate actual or intended *
// * publication of this file. *
// * *
// * NGLibraryCharacterizer, Development_version_64 - build 201405281900 *
// * *
// ******************************************************************************
//
// * Default delays
// * comb. path delay : 0.1
// * seq. path delay : 0.1
// * delay cells : 0.1
// * timing checks : 0.1
//
// * NTC Setup
// * Export NTC sections : true
// * Combine setup / hold : true
// * Combine recovery/removal: true
//
// * Extras
// * Export `celldefine : false
// * Export `timescale : -
//
`timescale 1ps/1ps
module AND2_X1 (A1, A2, Z);
input A1;
input A2;
output Z;
and(Z, A1, A2);
specify
(A1 => Z) = (0.1, 0.1);
(A2 => Z) = (0.1, 0.1);
endspecify
endmodule
module AND2_X2 (A1, A2, Z);
input A1;
input A2;
output Z;
and(Z, A1, A2);
specify
(A1 => Z) = (0.1, 0.1);
(A2 => Z) = (0.1, 0.1);
endspecify
endmodule
module AND3_X1 (A1, A2, A3, Z);
input A1;
input A2;
input A3;
output Z;
and(Z, i_16, A3);
and(i_16, A1, A2);
specify
(A1 => Z) = (0.1, 0.1);
(A2 => Z) = (0.1, 0.1);
(A3 => Z) = (0.1, 0.1);
endspecify
endmodule
module AND3_X2 (A1, A2, A3, Z);
input A1;
input A2;
input A3;
output Z;
and(Z, i_22, A3);
and(i_22, A1, A2);
specify
(A1 => Z) = (0.1, 0.1);
(A2 => Z) = (0.1, 0.1);
(A3 => Z) = (0.1, 0.1);
endspecify
endmodule
module AND4_X1 (A1, A2, A3, A4, Z);
input A1;
input A2;
input A3;
input A4;
output Z;
and(Z, i_8, A4);
and(i_8, i_9, A3);
and(i_9, A1, A2);
specify
(A1 => Z) = (0.1, 0.1);
(A2 => Z) = (0.1, 0.1);
(A3 => Z) = (0.1, 0.1);
(A4 => Z) = (0.1, 0.1);
endspecify
endmodule
module AND4_X2 (A1, A2, A3, A4, Z);
input A1;
input A2;
input A3;
input A4;
output Z;
and(Z, i_8, A4);
and(i_8, i_9, A3);
and(i_9, A1, A2);
specify
(A1 => Z) = (0.1, 0.1);
(A2 => Z) = (0.1, 0.1);
(A3 => Z) = (0.1, 0.1);
(A4 => Z) = (0.1, 0.1);
endspecify
endmodule
module ANTENNA (I);
input I;
endmodule
module AOI21_X1 (A1, A2, B, ZN);
input A1;
input A2;
input B;
output ZN;
not(ZN, i_26);
or(i_26, i_27, B);
and(i_27, A1, A2);
specify
(A1 => ZN) = (0.1, 0.1);
(A2 => ZN) = (0.1, 0.1);
if((~A1& ~A2)) (B => ZN) = (0.1, 0.1);
if((~A1 & A2)) (B => ZN) = (0.1, 0.1);
if((A1 & ~A2)) (B => ZN) = (0.1, 0.1);
endspecify
endmodule
module AOI21_X2 (A1, A2, B, ZN);
input A1;
input A2;
input B;
output ZN;
not(ZN, i_20);
or(i_20, i_21, B);
and(i_21, A1, A2);
specify
(A1 => ZN) = (0.1, 0.1);
(A2 => ZN) = (0.1, 0.1);
if((~A1 & ~A2)) (B => ZN) = (0.1, 0.1);
if((~A1 & A2)) (B => ZN) = (0.1, 0.1);
if((A1 & ~A2)) (B => ZN) = (0.1, 0.1);
endspecify
endmodule
module AOI22_X1 (A1, A2, B1, B2, ZN);
input A1;
input A2;
input B1;
input B2;
output ZN;
not(ZN, i_12);
or(i_12, i_13, i_14);
and(i_13, A1, A2);
and(i_14, B1, B2);
specify
if((A2 & ~B1 & ~B2)) (A1 => ZN) = (0.1, 0.1);
if((A2 & ~B1 & B2)) (A1 => ZN) = (0.1, 0.1);
if((A2 & B1 & ~B2)) (A1 => ZN) = (0.1, 0.1);
if((A1 & ~B1 & ~B2)) (A2 => ZN) = (0.1, 0.1);
if((A1 & ~B1 & B2)) (A2 => ZN) = (0.1, 0.1);
if((A1 & B1 & ~B2)) (A2 => ZN) = (0.1, 0.1);
if((~A1 & ~A2 & B2)) (B1 => ZN) = (0.1, 0.1);
if((~A1 & A2 & B2)) (B1 => ZN) = (0.1, 0.1);
if((A1 & ~A2 & B2)) (B1 => ZN) = (0.1, 0.1);
if((~A1 & ~A2 & B1)) (B2 => ZN) = (0.1, 0.1);
if((~A1 & A2 & B1)) (B2 => ZN) = (0.1, 0.1);
if((A1 & ~A2 & B1)) (B2 => ZN) = (0.1, 0.1);
endspecify
endmodule
module AOI22_X2 (A1, A2, B1, B2, ZN);
input A1;
input A2;
input B1;
input B2;
output ZN;
not(ZN, i_12);
or(i_12, i_13, i_14);
and(i_13, A1, A2);
and(i_14, B1, B2);
specify
if((A2 & ~B1 & ~B2)) (A1 => ZN) = (0.1, 0.1);
if((A2 & ~B1 & B2 )) (A1 => ZN) = (0.1, 0.1);
if((A2 & B1 & ~B2)) (A1 => ZN) = (0.1, 0.1);
if((A1 & ~B1 & ~B2)) (A2 => ZN) = (0.1, 0.1);
if((A1 & ~B1 & B2 )) (A2 => ZN) = (0.1, 0.1);
if((A1 & B1 & ~B2)) (A2 => ZN) = (0.1, 0.1);
if((~A1 & ~A2 & B2 )) (B1 => ZN) = (0.1, 0.1);
if((~A1 & A2 & B2 )) (B1 => ZN) = (0.1, 0.1);
if((A1 & ~A2 & B2 )) (B1 => ZN) = (0.1, 0.1);
if((~A1 & ~A2 & B1 )) (B2 => ZN) = (0.1, 0.1);
if((~A1 & A2 & B1 )) (B2 => ZN) = (0.1, 0.1);
if((A1 & ~A2 & B1 )) (B2 => ZN) = (0.1, 0.1);
endspecify
endmodule
module BUF_X1 (I, Z);
input I;
output Z;
buf(Z, I);
specify
(I => Z) = (0.1, 0.1);
endspecify
endmodule
module BUF_X2 (I, Z);
input I;
output Z;
buf(Z, I);
specify
(I => Z) = (0.1, 0.1);
endspecify
endmodule
module BUF_X4 (I, Z);
input I;
output Z;
buf(Z, I);
specify
(I => Z) = (0.1, 0.1);
endspecify
endmodule
module BUF_X8 (I, Z);
input I;
output Z;
buf(Z, I);
specify
(I => Z) = (0.1, 0.1);
endspecify
endmodule
module BUF_X12 (I, Z);
input I;
output Z;
buf(Z, I);
specify
(I => Z) = (0.1, 0.1);
endspecify
endmodule
module BUF_X16 (I, Z);
input I;
output Z;
buf(Z, I);
specify
(I => Z) = (0.1, 0.1);
endspecify
endmodule
module CLKBUF_X1 (I, Z);
input I;
output Z;
buf(Z, I);
specify
(I => Z) = (0.1, 0.1);
endspecify
endmodule
module CLKBUF_X2 (I, Z);
input I;
output Z;
buf(Z, I);
specify
(I => Z) = (0.1, 0.1);
endspecify
endmodule
module CLKBUF_X4 (I, Z);
input I;
output Z;
buf(Z, I);
specify
(I => Z) = (0.1, 0.1);
endspecify
endmodule
module CLKBUF_X8 (I, Z);
input I;
output Z;
buf(Z, I);
specify
(I => Z) = (0.1, 0.1);
endspecify
endmodule
module CLKBUF_X12 (I, Z);
input I;
output Z;
buf(Z, I);
specify
(I => Z) = (0.1, 0.1);
endspecify
endmodule
module CLKBUF_X16 (I, Z);
input I;
output Z;
buf(Z, I);
specify
(I => Z) = (0.1, 0.1);
endspecify
endmodule
module LS_LH_40_X1 (A, Z);
input A;
output Z;
buf(Z, A);
specify
(A => Z) = (0.1, 0.1);
endspecify
endmodule
module LS_LH_45_X1 (A, Z);
input A;
output Z;
buf(Z, A);
specify
(A => Z) = (0.1, 0.1);
endspecify
endmodule
module LS_LH_50_X1 (A, Z);
input A;
output Z;
buf(Z, A);
specify
(A => Z) = (0.1, 0.1);
endspecify
endmodule
module LS_LH_55_X1 (A, Z);
input A;
output Z;
buf(Z, A);
specify
(A => Z) = (0.1, 0.1);
endspecify
endmodule
module LS_LH_60_X1 (A, Z);
input A;
output Z;
buf(Z, A);
specify
(A => Z) = (0.1, 0.1);
endspecify
endmodule
module LS_LH_65_X1 (A, Z);
input A;
output Z;
buf(Z, A);
specify
(A => Z) = (0.1, 0.1);
endspecify
endmodule
module LS_LH_70_X1 (A, Z);
input A;
output Z;
buf(Z, A);
specify
(A => Z) = (0.1, 0.1);
endspecify
endmodule
module LS_LH_75_X1 (A, Z);
input A;
output Z;
buf(Z, A);
specify
(A => Z) = (0.1, 0.1);
endspecify
endmodule
primitive \seq_CLKGATETST_X1 (QD, CLK, nextstate, NOTIFIER);
output QD;
input CLK;
input nextstate;
input NOTIFIER;
reg QD;
table
// CLK nextstate NOTIFIER : @QD : QD
0 0 ? : ? : 0;
0 1 ? : ? : 1;
1 ? ? : ? : -; // Ignore non-triggering clock edge
? * ? : ? : -; // Ignore all edges on nextstate
? ? * : ? : x; // Any NOTIFIER change
endtable
endprimitive
module CLKGATETST_X1 (CLK, E, TE, Q);
input CLK;
input E;
input TE;
output Q;
reg NOTIFIER;
`ifdef NTC
and(Q, CLK_d, QD);
\seq_CLKGATETST_X1 (QD, CLK_d, nextstate, NOTIFIER);
not(QDn, QD);
or(nextstate, E_d, TE_d);
`else
and(Q, CLK, QD);
\seq_CLKGATETST_X1 (QD, CLK, nextstate, NOTIFIER);
not(QDn, QD);
or(nextstate, E, TE);
`endif
specify
if((E == 1'b0) && (TE == 1'b0)) (negedge CLK => (Q +: 1'b0)) = (0.1, 0.1);
if((E == 1'b0) && (TE == 1'b1)) (CLK => Q) = (0.1, 0.1);
if((E == 1'b1) && (TE == 1'b0)) (CLK => Q) = (0.1, 0.1);
if((E == 1'b1) && (TE == 1'b1)) (CLK => Q) = (0.1, 0.1);
`ifdef NTC
$setuphold(posedge CLK, negedge E, 0.1, 0.1, NOTIFIER, , ,CLK_d, E_d);
$setuphold(posedge CLK, negedge TE, 0.1, 0.1, NOTIFIER, , ,CLK_d, TE_d);
$setuphold(posedge CLK, posedge E, 0.1, 0.1, NOTIFIER, , ,CLK_d, E_d);
$setuphold(posedge CLK, posedge TE, 0.1, 0.1, NOTIFIER, , ,CLK_d, TE_d);
$width(negedge CLK, 0.1, 0, NOTIFIER);
`else
$setuphold(posedge CLK, negedge E, 0.1, 0.1, NOTIFIER);
$setuphold(posedge CLK, negedge TE, 0.1, 0.1, NOTIFIER);
$setuphold(posedge CLK, posedge E, 0.1, 0.1, NOTIFIER);
$setuphold(posedge CLK, posedge TE, 0.1, 0.1, NOTIFIER);
$width(negedge CLK, 0.1, 0, NOTIFIER);
`endif
endspecify
endmodule
primitive \seq_DFFRNQ_X1 (IQ, RN, nextstate, CLK, NOTIFIER);
output IQ;
input RN;
input nextstate;
input CLK;
input NOTIFIER;
reg IQ;
table
// RN nextstate CLK NOTIFIER : @IQ : IQ
? 0 r ? : ? : 0;
1 1 r ? : ? : 1;
? 0 * ? : 0 : 0; // reduce pessimism
1 1 * ? : 1 : 1; // reduce pessimism
1 * ? ? : ? : -; // Ignore all edges on nextstate
1 ? n ? : ? : -; // Ignore non-triggering clock edge
0 ? ? ? : ? : 0; // RN activated
* ? ? ? : 0 : 0; // Cover all transitions on RN
? ? ? * : ? : x; // Any NOTIFIER change
endtable
endprimitive
module DFFRNQ_X1 (D, RN, CLK, Q);
input D;
input RN;
input CLK;
output Q;
reg NOTIFIER;
`ifdef NTC
`ifdef RECREM
buf (RN_d, RN_di);
`else
buf (RN_d, RN);
`endif
\seq_DFFRNQ_X1 (IQ, RN_d, nextstate, CLK_d, NOTIFIER);
not(IQN, IQ);
buf(Q, IQ);
buf(nextstate, D_d);
// Delayed data/reference logic
buf(id_5, RN_d);
`ifdef TETRAMAX
`else
ng_xbuf(xid_5, id_5, 1'b1);
`endif
`else
\seq_DFFRNQ_X1 (IQ, RN, nextstate, CLK, NOTIFIER);
not(IQN, IQ);
buf(Q, IQ);
buf(nextstate, D);
// Delayed data/reference logic
buf(id_4, RN);
`ifdef TETRAMAX
`else
ng_xbuf(xid_4, id_4, 1'b1);
`endif
`endif
specify
(posedge CLK => (Q +: D)) = (0.1, 0.1);
if((CLK == 1'b0) && (D == 1'b0)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1);
if((CLK == 1'b0) && (D == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1);
if((CLK == 1'b1) && (D == 1'b0)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1);
if((CLK == 1'b1) && (D == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1);
`ifdef NTC
`ifdef RECREM
$recrem(posedge RN, posedge CLK, 0.1, 0.1, NOTIFIER, , ,RN_di, CLK_d);
`else
$hold(posedge CLK, posedge RN, 0.1, NOTIFIER);
$recovery(posedge RN, posedge CLK, 0.1, NOTIFIER);
`endif
$setuphold(posedge CLK &&& (xid_5), negedge D, 0.1, 0.1, NOTIFIER, , ,CLK_d, D_d);
$setuphold(posedge CLK &&& (xid_5), posedge D, 0.1, 0.1, NOTIFIER, , ,CLK_d, D_d);
$width(negedge CLK &&& (xid_5), 0.1, 0, NOTIFIER);
$width(negedge RN, 0.1, 0, NOTIFIER);
$width(posedge CLK &&& (xid_5), 0.1, 0, NOTIFIER);
`else
$hold(posedge CLK, posedge RN, 0.1, NOTIFIER);
$recovery(posedge RN, posedge CLK, 0.1, NOTIFIER);
$setuphold(posedge CLK &&& (xid_4), negedge D, 0.1, 0.1, NOTIFIER);
$setuphold(posedge CLK &&& (xid_4), posedge D, 0.1, 0.1, NOTIFIER);
$width(negedge CLK &&& (xid_4), 0.1, 0, NOTIFIER);
$width(negedge RN, 0.1, 0, NOTIFIER);
$width(posedge CLK &&& (xid_4), 0.1, 0, NOTIFIER);
`endif
endspecify
endmodule
primitive \seq_DFFSNQ_X1 (IQ, SN, nextstate, CLK, NOTIFIER);
output IQ;
input SN;
input nextstate;
input CLK;
input NOTIFIER;
reg IQ;
table
// SN nextstate CLK NOTIFIER : @IQ : IQ
1 0 r ? : ? : 0;
? 1 r ? : ? : 1;
1 0 * ? : 0 : 0; // reduce pessimism
? 1 * ? : 1 : 1; // reduce pessimism
1 * ? ? : ? : -; // Ignore all edges on nextstate
1 ? n ? : ? : -; // Ignore non-triggering clock edge
0 ? ? ? : ? : 1; // SN activated
* ? ? ? : 1 : 1; // Cover all transitions on SN
? ? ? * : ? : x; // Any NOTIFIER change
endtable
endprimitive
module DFFSNQ_X1 (D, SN, CLK, Q);
input D;
input SN;
input CLK;
output Q;
reg NOTIFIER;
`ifdef NTC
`ifdef RECREM
buf (SN_d, SN_di);
`else
buf (SN_d, SN);
`endif
\seq_DFFSNQ_X1 (IQ, SN_d, nextstate, CLK_d, NOTIFIER);
not(IQN, IQ);
buf(Q, IQ);
buf(nextstate, D_d);
// Delayed data/reference logic
buf(id_5, SN_d);
`ifdef TETRAMAX
`else
ng_xbuf(xid_5, id_5, 1'b1);
`endif
`else
\seq_DFFSNQ_X1 (IQ, SN, nextstate, CLK, NOTIFIER);
not(IQN, IQ);
buf(Q, IQ);
buf(nextstate, D);
// Delayed data/reference logic
buf(id_4, SN);
`ifdef TETRAMAX
`else
ng_xbuf(xid_4, id_4, 1'b1);
`endif
`endif
specify
(posedge CLK => (Q +: D)) = (0.1, 0.1);
if((CLK == 1'b0) && (D == 1'b0)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);
if((CLK == 1'b0) && (D == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);
if((CLK == 1'b1) && (D == 1'b0)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);
if((CLK == 1'b1) && (D == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);
`ifdef NTC
`ifdef RECREM
$recrem(posedge SN, posedge CLK, 0.1, 0.1, NOTIFIER, , ,SN_di, CLK_d);
`else
$hold(posedge CLK, posedge SN, 0.1, NOTIFIER);
$recovery(posedge SN, posedge CLK, 0.1, NOTIFIER);
`endif
$setuphold(posedge CLK &&& (xid_5), negedge D, 0.1, 0.1, NOTIFIER, , ,CLK_d, D_d);
$setuphold(posedge CLK &&& (xid_5), posedge D, 0.1, 0.1, NOTIFIER, , ,CLK_d, D_d);
$width(negedge CLK &&& (xid_5), 0.1, 0, NOTIFIER);
$width(negedge SN, 0.1, 0, NOTIFIER);
$width(posedge CLK &&& (xid_5), 0.1, 0, NOTIFIER);
`else
$hold(posedge CLK, posedge SN, 0.1, NOTIFIER);
$recovery(posedge SN, posedge CLK, 0.1, NOTIFIER);
$setuphold(posedge CLK &&& (xid_4), negedge D, 0.1, 0.1, NOTIFIER);
$setuphold(posedge CLK &&& (xid_4), posedge D, 0.1, 0.1, NOTIFIER);
$width(negedge CLK &&& (xid_4), 0.1, 0, NOTIFIER);
$width(negedge SN, 0.1, 0, NOTIFIER);
$width(posedge CLK &&& (xid_4), 0.1, 0, NOTIFIER);
`endif
endspecify
endmodule
module FA_X1 (A, B, CI, CO, S);
input A;
input B;
input CI;
output CO;
output S;
or(CO, i_84, i_87);
or(i_84, i_85, i_86);
and(i_85, B, CI);
and(i_86, B, A);
and(i_87, CI, A);
not(S, i_92);
or(i_92, i_93, i_99);
and(i_93, i_94, A);
not(i_94, i_95);
or(i_95, i_96, i_97);
and(i_96, B, CI);
not(i_97, i_98);
or(i_98, B, CI);
not(i_99, i_100);
or(i_100, i_101, A);
not(i_101, i_102);
or(i_102, i_103, i_104);
and(i_103, B, CI);
not(i_104, i_105);
or(i_105, B, CI);
specify
if((B == 1'b0) && (CI == 1'b1)) (A => CO) = (0.1, 0.1);
if((B == 1'b1) && (CI == 1'b0)) (A => CO) = (0.1, 0.1);
if((A == 1'b0) && (CI == 1'b1)) (B => CO) = (0.1, 0.1);
if((A == 1'b1) && (CI == 1'b0)) (B => CO) = (0.1, 0.1);
if((A == 1'b0) && (B == 1'b1)) (CI => CO) = (0.1, 0.1);
if((A == 1'b1) && (B == 1'b0)) (CI => CO) = (0.1, 0.1);
if((B == 1'b0) && (CI == 1'b0)) (A => S) = (0.1, 0.1);
if((B == 1'b0) && (CI == 1'b1)) (A => S) = (0.1, 0.1);
if((B == 1'b1) && (CI == 1'b0)) (A => S) = (0.1, 0.1);
if((B == 1'b1) && (CI == 1'b1)) (A => S) = (0.1, 0.1);
if((A == 1'b0) && (CI == 1'b0)) (B => S) = (0.1, 0.1);
if((A == 1'b0) && (CI == 1'b1)) (B => S) = (0.1, 0.1);
if((A == 1'b1) && (CI == 1'b0)) (B => S) = (0.1, 0.1);
if((A == 1'b1) && (CI == 1'b1)) (B => S) = (0.1, 0.1);
if((A == 1'b0) && (B == 1'b0)) (CI => S) = (0.1, 0.1);
if((A == 1'b0) && (B == 1'b1)) (CI => S) = (0.1, 0.1);
if((A == 1'b1) && (B == 1'b0)) (CI => S) = (0.1, 0.1);
if((A == 1'b1) && (B == 1'b1)) (CI => S) = (0.1, 0.1);
endspecify
endmodule
module FILLTIE ();
endmodule
module FILL_X1 ();
endmodule
module FILL_X2 ();
endmodule
module FILL_X4 ();
endmodule
module FILL_X8 ();
endmodule
module FILL_X16 ();
endmodule
module HA_X1 (A, B, CO, S);
input A;
input B;
output CO;
output S;
and(CO, A, B);
not(S, i_58);
or(i_58, i_59, i_60);
and(i_59, A, B);
not(i_60, i_61);
or(i_61, A, B);
specify
(A => CO) = (0.1, 0.1);
(B => CO) = (0.1, 0.1);
if((B == 1'b0)) (A => S) = (0.1, 0.1);
if((B == 1'b1)) (A => S) = (0.1, 0.1);
if((A == 1'b0)) (B => S) = (0.1, 0.1);
if((A == 1'b1)) (B => S) = (0.1, 0.1);
endspecify
endmodule
module INV_X1 (I, ZN);
input I;
output ZN;
not(ZN, I);
specify
(I => ZN) = (0.1, 0.1);
endspecify
endmodule
module INV_X2 (I, ZN);
input I;
output ZN;
not(ZN, I);
specify
(I => ZN) = (0.1, 0.1);
endspecify
endmodule
module INV_X4 (I, ZN);
input I;
output ZN;
not(ZN, I);
specify
(I => ZN) = (0.1, 0.1);
endspecify
endmodule
module INV_X8 (I, ZN);
input I;
output ZN;
not(ZN, I);
specify
(I => ZN) = (0.1, 0.1);
endspecify
endmodule
module INV_X12 (I, ZN);
input I;
output ZN;
not(ZN, I);
specify
(I => ZN) = (0.1, 0.1);
endspecify
endmodule
module INV_X16 (I, ZN);
input I;
output ZN;
not(ZN, I);
specify
(I => ZN) = (0.1, 0.1);
endspecify
endmodule
primitive \seq_LHQ_X1 (IQ, nextstate, E, NOTIFIER);
output IQ;
input nextstate;
input E;
input NOTIFIER;
reg IQ;
table
// nextstate E NOTIFIER : @IQ : IQ
0 1 ? : ? : 0;
1 1 ? : ? : 1;
* ? ? : ? : -; // Ignore all edges on nextstate
? 0 ? : ? : -; // Ignore non-triggering clock edge
? ? * : ? : x; // Any NOTIFIER change
endtable
endprimitive
module LHQ_X1 (D, E, Q);
input D;
input E;
output Q;
reg NOTIFIER;
`ifdef NTC
\seq_LHQ_X1 (IQ, nextstate, E_d, NOTIFIER);
not(IQN, IQ);
buf(Q, IQ);
buf(nextstate, D_d);
`else
\seq_LHQ_X1 (IQ, nextstate, E, NOTIFIER);
not(IQN, IQ);
buf(Q, IQ);
buf(nextstate, D);
`endif
specify
(D => Q) = (0.1, 0.1);
(posedge E => (Q +: D)) = (0.1, 0.1);
`ifdef NTC
$setuphold(negedge E, negedge D, 0.1, 0.1, NOTIFIER, , ,E_d, D_d);
$setuphold(negedge E, posedge D, 0.1, 0.1, NOTIFIER, , ,E_d, D_d);
$width(posedge E, 0.1, 0, NOTIFIER);
`else
$setuphold(negedge E, negedge D, 0.1, 0.1, NOTIFIER);
$setuphold(negedge E, posedge D, 0.1, 0.1, NOTIFIER);
$width(posedge E, 0.1, 0, NOTIFIER);
`endif
endspecify
endmodule
module MUX2_X1 (I0, I1, S, Z);
input I0;
input I1;
input S;
output Z;
or(Z, i_24, i_25);
and(i_24, S, I1);
and(i_25, i_26, I0);
not(i_26, S);
specify
if((I1 == 1'b0) && (S == 1'b0)) (I0 => Z) = (0.1, 0.1);
if((I1 == 1'b1) && (S == 1'b0)) (I0 => Z) = (0.1, 0.1);
if((I0 == 1'b0) && (S == 1'b1)) (I1 => Z) = (0.1, 0.1);
if((I0 == 1'b1) && (S == 1'b1)) (I1 => Z) = (0.1, 0.1);
if((I0 == 1'b0) && (I1 == 1'b1)) (S => Z) = (0.1, 0.1);
if((I0 == 1'b1) && (I1 == 1'b0)) (S => Z) = (0.1, 0.1);
endspecify
endmodule
module NAND2_X1 (A1, A2, ZN);
input A1;
input A2;
output ZN;
not(ZN, i_28);
and(i_28, A1, A2);
specify
(A1 => ZN) = (0.1, 0.1);
(A2 => ZN) = (0.1, 0.1);
endspecify
endmodule
module NAND2_X2 (A1, A2, ZN);
input A1;
input A2;
output ZN;
not(ZN, i_22);
and(i_22, A1, A2);
specify