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DDC.script
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DDC.script
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remove_design -all
set power_preserve_rtl_hier_names "true"
set search_path "/home/home2/students/afzalikusha/CGRA/Multiplier_Ref/Dadda_PPAM_1_3/ModelsimFiles/"
define_design_lib work -path "work"
set topname "dadda_PPAM_1_3"
#***********************************************
#*Reading Libraries
#***********************************************
read_file "/home/home2/students/afzalikusha/ScaledLibraries/Library_Date_19/nanGate_ccs_15_LS.db"
#read_file "/home/home2/students/afzalikusha/NangateLibrary15nm/15nmFinFET.db "
set link_library "/home/home2/students/afzalikusha/ScaledLibraries/Library_Date_19/nanGate_ccs_15_LS.db"
#set link_library "/home/home2/students/afzalikusha/NangateLibrary15nm/15nmFinFET.db "
set target_library "/home/home2/students/afzalikusha/ScaledLibraries/Library_Date_19/nanGate_ccs_15_LS.db"
#set target_library "/home/home2/students/afzalikusha/NangateLibrary15nm/15nmFinFET.db "
list_libs
#***********************************************
#*
#***********************************************
read_ddc Dadda_PPAM_1_3.ddc
current_design $topname
read_saif -input hassansaif_3_exact.saif -instance_name Test_DADDA_8bit_All_Input/uut1
##for below command: at first you should simulate the circit with zero delay. After that, DC will give a minimum delay.
#Then you should put the minimum delay instead of zero till met the constraints.
set_max_delay 2.500 -from [ get_ports -filter {@port_direction == in}] -to [ get_ports -filter {@port_direction == out}]
#***********************************************
#*Setting Conditions
#***********************************************
##################################
#compile
###################################
#compile
###########################################################################################################
## you should create a folder with outputs name in your simulation path. This make the simulation easier.
###########################################################################################################
###########################################################################################################
##Reports
###########################################################################################################
report_timing -path full -delay max -max_paths 10 -nworst 1 > "~/CGRA/Multiplier_Ref/Dadda_PPAM_1_3/Reports_DDC/dadda_Dadda_PPAM_1_3_timing.report"
report_constraint -all_violators > "~/CGRA/Multiplier_Ref/Dadda_PPAM_1_3/Reports_DDC/dadda_Dadda_PPAM_1_3_constraint.report"
report_power -hierarchy > "~/CGRA/Multiplier_Ref/Dadda_PPAM_1_3/Reports_DDC/dadda_Dadda_PPAM_1_3_power.report"
report_power -cell > "~/CGRA/Multiplier_Ref/Dadda_PPAM_1_3/Reports_DDC/dadda_Dadda_PPAM_1_3_power_Cell.report"
report_area > "~/CGRA/Multiplier_Ref/Dadda_PPAM_1_3/Reports_DDC/dadda_Dadda_PPAM_1_3_area.report"
exit