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ROADMAP.md

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ZenithSoC Roadmap

The project will be developed using an incremental approach, structured into four distinct phases. Each phase builds upon the functionality established in the preceding step, progressively enhancing the platform capabilities. Notably, these phases are designed to be modular, allowing for any configuration to operate independently without dependency on subsequent additions. Here’s the phased development plan:

Basic Configuration Features

  • CPU 100MHz
  • Interrupt Controller
  • On Chip Memory
  • Boot ROM
  • GPIO
  • Timers
  • UART
  • Single Master AXI Interconnection Network

Microcontroller Configuration Features

  • CPU 100MHz
  • Interrupt Controller
  • On Chip Memory
  • Boot ROM
  • GPIO
  • Timers
  • UART
  • SPI
  • I²C
  • I²S
  • Ethernet
  • PRNG
  • Single Master AXI Interconnection Network

Microprocessor Configuration Features

  • CPU 100MHz
  • Interrupt Controller
  • On Chip Memory
  • Boot ROM
  • GPIO
  • Timers
  • UART
  • SPI
  • I²C
  • I²S
  • Ethernet
  • PRNG
  • Single Master AXI Interconnection Network
  • Data and Instruction Cache
  • DMA
  • DDR2 Controller

SoC Configuration Features

  • CPU 100MHz
  • Interrupt Controller
  • On Chip Memory
  • Boot ROM
  • GPIO
  • Timers
  • UART
  • SPI
  • I²C
  • I²S
  • Ethernet
  • PRNG
  • Single Master AXI Interconnection Network
  • Data and Instruction Cache
  • DMA
  • DDR2 Controller
  • Audio System (APU)
  • Video System (GPU)