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DPDK initialization freezes if dpdk_corelist does not contain 0
bug
Documentation
#552
opened Jan 31, 2022 by
sinddennhierschonallenamenvergeben
Python API - RX timeouts when radio is idle for a little while
bug
#418
opened Mar 2, 2021 by
Djgreene730
USRP X440 with X4_1600: Overflow recording data using Replay Block
bug
X440
#737
opened Mar 27, 2024 by
mmatthebi
B2xx Repeated transmit decaying amplitudes starting with 4.5.0
#751
opened May 13, 2024 by
thomasteisberg
rx_stream for 8 bit samples not working all the times when uisng c++
B210
bug
X3x0
#711
opened Nov 2, 2023 by
MikoMikarro
Vitis HLS C-Synthesis Fails on Project in UHD 4.5, 4.6, and Master Subdirectories
bug
RFNoC
#724
opened Feb 1, 2024 by
superdavid101
X3x0 - repeatedly setting sync source to external delays FPGA time
bug
X3x0
#699
opened Aug 30, 2023 by
mmatthebi
rfnoc_create_verilog.py module I/O port in RFNoC >=4.0: Add feature to generate IO ports.
Feature Request
#605
opened Jun 23, 2022 by
andreaskuster
Clock or time source can be silently altered by UHD on N3xx
bug
#556
opened Feb 7, 2022 by
draeman-synoptic
host: rfnoc_replay_samples_from_file.cpp add multi-channel support
Feature Request
#749
opened May 9, 2024 by
urima
Intermittent USB Connectivity Issue on Boot and Shutdown with SDR B210 Device
B2xx Series
B210
bug
#742
opened Apr 18, 2024 by
YosefCohen877
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