using vivado ip core in rfnocmod tool

[vahidrezaee]

Title: Unable to Change Read-Only Property "synth" when Building Out-of-Tree RFNoC Module with Vivado IP Cores for X410 Device

Issue Description:
I am attempting to build an out-of-tree (OOT) RFNoC module using Vivado IP cores in my project. To create the project, I utilized the rfnocmodtool tool and followed a similar structure to the rfnoc-example folder located in /uhd/host/example/rfnoc-example. I have made necessary modifications to the Makefiles and CMakeLists.txt files in the project.

In the Verilog file within my RFNoC block, I have instantiated two Vivado IP cores. However, during the FPGA image build process for the X410 device, I encounter the following error: "ERROR: [Common 17-107] Cannot change read-only property 'generate_synth_checkpoint'."

Steps to Reproduce:

1. Use rfnocmodtool to create a project for an out-of-tree RFNoC module.
2. Modify the Makefiles and CMakeLists.txt files as per the structure in /uhd/host/example/rfnoc-example.
3. Instantiate two Vivado IP cores in the RFNoC block Verilog file.
4. Attempt to build the FPGA image for the X410 device.

Expected Behavior:
The build process should complete successfully without encountering any errors related to read-only properties.

Actual Behavior:
The build process fails with the error message: "ERROR: [Common 17-107] Cannot change read-only property 'generate_synth_checkpoint'."

Environment:

• Operating System: [ubutu 20]
• Vivado Version: [2021.1]
• RFNoC Version: [ RFNoC 4]
• X410 Device: [ the X410 device]

Additional Information:

• Attach relevant portions of the Verilog file where Vivado IP cores are instantiated.
• Include snippets from the modified Makefiles and CMakeLists.txt files.
• Provide any additional details or configurations that might be relevant to the issue.
  

Screenshots/Logs:
Include any relevant screenshots or log outputs that capture the error message and its context during the build process.

[2444616578]

When I use rfnocmodtool to creat a self-build module, I did not modify Cmakelist.txt. When using the command"rfnocmodttol add ", the Cmakelist is changed automatically. I do not know whether you use the 'add' command ., If not I recommand it to you . If you have used it, I suppose you not to change Cmakelist.txt. Just follow the "get start with RFNoC" and "RFNoC 4.0", the two websites. And I suggest you that you should check you verilog.v file. You may have some unrealizable functions in it. Make sure that you have modified XXX.yml, nlock_XXX.yml, et. al. rightly

[vahidrezaee]

I did something interesting.
I create a simple oot module by rfnocmodtool.
when I want to build the FPGA image core, I use project mode by adding "GUI=1 CHECK=1" to make command,
after vivado opens I navigate to my oot module code and add vivado IP core as many as I want.
for example for my x410_200_rfnoc_image_core.yml

make  x410_200_rfnoc_image_core GUI=1 CHECK=1

[feyzaozdemir]

Hi @vahidrezaee

If this method works, can you explain the steps in detail? Thank you.