This repository has been archived by the owner on Jan 20, 2023. It is now read-only.

Commits

Commits on Jul 22, 2022

Commits on Jun 26, 2022

Added setters to SplitWord16
DrItanium
committedJun 26, 2022
Make sure that we write 16-bits on each bus cycle at a time
DrItanium
committedJun 26, 2022
Finished up separating reads into multiple separate parts
DrItanium
committedJun 26, 2022
Serial0 fixed up
DrItanium
committedJun 26, 2022
16/32 reads for sd card interface
DrItanium
committedJun 26, 2022
RTC and Display interface updates
DrItanium
committedJun 26, 2022
Add 16 and 32-bit read operations for external devices
DrItanium
committedJun 26, 2022

Commits on Jun 25, 2022

Repurpose BURST NEXT during the cycle itself to be a blast pin passthrough.
DrItanium
committedJun 25, 2022
Try waiting for do cycle to be deasserted before continuing after asserting ready
DrItanium
committedJun 25, 2022
Delete decodeAndExecuteExternalDeviceWrite16
DrItanium
committedJun 25, 2022
Reroute more code to go through the new interface
DrItanium
committedJun 25, 2022
Delete the old write method
DrItanium
committedJun 25, 2022
Rewrite sd card interface to use the three widths of 32-bit writes
DrItanium
committedJun 25, 2022
Do external device write operation decoding to make sure that we select the correct stuff
DrItanium
committedJun 25, 2022
Remove debugging code from external device handlers
DrItanium
committedJun 25, 2022
Added wrapper routines for getting 32-bit words from the cache
DrItanium
committedJun 25, 2022
Make sure we advance the address pointer by one when storing the upper 16 bits of a 32-bit quantity
DrItanium
committedJun 25, 2022
Operate on SplitWord16 values but also make sure that we can set 32-bit values in the cache fairly easily
DrItanium
committedJun 25, 2022
Revert LoadStoreStyle but implement 32-bit reads in a fairly simple fashion to start
DrItanium
committedJun 25, 2022
Expand LoadStoreStyle out to 16 states
DrItanium
committedJun 25, 2022
Forgot to merge the reference mark fixes for type3
DrItanium
committedJun 25, 2022

Commits on Apr 10, 2022

Typo fix
DrItanium
committedApr 10, 2022
Eliminate a template parameter from cache description
DrItanium
committedApr 10, 2022

Commits on Apr 9, 2022

Use the common bit set table to increase my sanity
DrItanium
committedApr 9, 2022
Merge all of the rand plru cache entries into a single file for simplicity
DrItanium
committedApr 9, 2022
Various fixes
DrItanium
committedApr 9, 2022
Fix some sizing issues
DrItanium
committedApr 9, 2022

Commits on Apr 8, 2022

Use a 10 way cache impl to increase the cache size
DrItanium
committedApr 8, 2022
Add a 10 way cache impl
DrItanium
committedApr 8, 2022
Add a 12 way entry
DrItanium
committedApr 8, 2022
Enable 14:128 for now
DrItanium
committedApr 8, 2022