{"payload":{"header_redesign_enabled":false,"results":[{"id":"148385735","archived":false,"color":"#adb2cb","followers":158,"has_funding_file":false,"hl_name":"Domipheus/RPU","hl_trunc_description":"Basic RISC-V CPU implementation in VHDL.","language":"VHDL","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":148385735,"name":"RPU","owner_id":6495819,"owner_login":"Domipheus","updated_at":"2020-09-13T21:02:10.026Z","has_issues":true}},"sponsorable":false,"topics":["cpu","fpga","vhdl","riscv","risc-v","apache2-license"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":69,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253ADomipheus%252FRPU%2B%2Blanguage%253AVHDL","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/Domipheus/RPU/star":{"post":"Gah6QYasRwvv-fg_Y_CQ-WAIi81mdER3Ovd-mFC6q4VENrhG0K4z8BEb5BXQVr4mIxxnRmUQbgdKAlW2Qyw6Ig"},"/Domipheus/RPU/unstar":{"post":"j9MWXce2pYT8LtXR3L48WMccIAwp-VamqYG5jfWqsBpTSQSDOhsqrK2WdwuQlBSrJXRHhFjYzdVUX1HxwA1Xcw"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"7kTZ-LG3nXW7zzN8UBKLGooRvXuh98il-lW_FQbp339IMlXSITGJQ5JchdTFYmcAp1eKavSD0pV0s7NaHj0fkg"}}},"title":"Repository search results"}