🌱 Open source ecosystem for open FPGA boards

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

Builds, flow and designs for the alpha release

FPGA based modular synth.

My first successful attempt on building a RISC-V CPU.

An 8-bit adder-subtractor made of full adders in Verilog

An ALU written in Verilog.