This is a 4-bit pipelined carry-ripple adder. The design has been optimized for delay. To view the project, download the zip file and open the project in Cadence Virtuoso.
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Updated
Apr 15, 2022
This is a 4-bit pipelined carry-ripple adder. The design has been optimized for delay. To view the project, download the zip file and open the project in Cadence Virtuoso.
Some codes I have implemented during my 10 day Training under VLSI DOMAIN
NGspice netlist files for simulation of analog and digital circuits.
BRACU CSE460 Lab (Summer 2020)
Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator
Universal Shift Register is a register which can be configured to load and/or retrieve the data in any mode (either serial or parallel) by shifting it either towards right or towards left. In other words, a combined design of unidirectional (either right- or left-shift of data bits as in case of SISO, SIPO, PISO, PIPO) and bidirectional shift re…
This is a basic project of Arithmetic Logic Unit that takes two input of 8 Bits each and undergoes 8 different operations and generates an output of 16 Bits
A full adder circuit is central to most digital circuits that perform addition or subtraction. It is so called because it adds together two binary digits, plus a carry-in digit to produce a sum and carry-out digit.1 It therefore has three inputs and two outputs.
This repository contains code files for VLSI Laboratory - EC39004, conducted in Spring 2024 at IIT Kharagpur
I've delved into leveraging my academic prowess to drive projects that contribute to my career advancement.
VLSI Conference Dates
Contains my resume
A compilation of various projects programmed fully in Verilog.
Interfacing of FPGA & HPS on DE1-SoC.
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers on FPGAs
Combinatorial and Decision Making (CDMO) project (AY 2021/2022)
This is the Repository which contains the detail of my work done at SCL Mohali (formerly Department of Space, ISRO). This was the internship basically focused on the "Experimental Analysis of MOS Capacitor for Oxide Furnaces" and further study of VLSI.
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